1. Field of the Invention
This invention relates to an improved plastic package for integrated circuit structures. More particularly, this invention relates to an improved plastic package for an integrated circuit structure which provides both heat dissipation and low ground bounce noise.
2. Description of the Related Art
In the conventional plastic-encapsulated packaging of integrated circuit structures, the die is conventionally attached to the center paddle of a metal lead frame which has a plurality of metal leads which fan out from a series of bonding pads arranged around the four sides of the die.
However, many high frequency and high power dissipating devices cannot be packaged into a plastic package due to ground noise and heat dissipation. The problem of heat dissipation has been addressed in plastic packaging by placing a heat spreader in a mold which improves the heat characteristics. For example, in Butt U.S. Pat. No. 4,410,927, which teaches a casing for an electrical component such as an integrated circuit die, a metal base member is provided onto which the die is bonded using an epoxy adhesive. A lead frame is also sealed and bonded to the metal base member. Daniels et al U.S. Pat. No. 4,680,613 discloses a low impedance package for an integrated circuit die comprising a lead frame without a central paddle and a ground plate which forms the die attach plate and which is spaced from and parallel to the lead frame. A dielectric layer is formed between the lead frame and the ground plate.
It is also, of course, known to use printed circuit structures as a part of the lead frame structure, both in ceramic and non-ceramic packaging. For example, Crane et al U.S. Pat. No. 3,838,984 discloses a printed circuit lead frame for an integrated circuit structure which comprises an insulating sheet member with a plurality of inner via holes arranged in a pattern to match that of terminal contacts on a chip and a plurality of outer via holes arranged in a pattern to match terminal pads on a supporting substrate. Raised contacts or bumps in each of the inner and outer via holes extend beyond one surface to make a conductively bonded contact with the terminal pads on the chip and substrate. Printed circuit leads on the other surface intercouple pairs of outer and inner contacts to complete electrical coupling of the chip to the substrate.
Honn et al U.S. Pat. No. 4,074,342 describes an electrical package for LSI devices which comprises a carrier comprising a number of pins encapsulated in an organic materials with both ends of the pins protruding. One end of the pins may serve as connectors to a circuit transposer which may be either a semiconductor or an insulator which may have suitably disposed diffusions or deposited metal as conductive paths to link the attached semiconductor devices to the pins.
Gogal U.S. Pat. No. 4,288,841 teaches a double cavity ceramic chip carrier which comprises a multilayer ceramic sandwich with metallization patterns defined on the horizontal surfaces of each of a plurality of such ceramic layers.
Desai et al U.S. Pat. No. 4,407,007 describe a ceramic substrate comprising a series of laminated ceramic sheets with a semiconductor device mounted on the top surface of the substrate, I/O connections such as pins on the bottom surface, and an internal metallurgy system formed of printed conductive circuit patterns and filled vias on and in the sheets.
Miyauchi et al U.S. Pat. No. 4,725,878 describes a semiconductor device comprising an integrated circuit die mounted on a multilayer of insulative substrates with high speed signal leads having portions formed on the side surfaces of the package. Portions of the signal lines also comprise interlayers between the insulating substrates and part of the signal lines comprise wire through via holes in the substrates.
In Hayward et al U.S. Pat. No. 4,801,999, which is assigned to the assignee of this invention, there is shown a lead assembly in which leads and busses are arranged on both sides of a dielectric layer.
However, when such printed circuit layers are used in the package, a heat sink is usually not attached directly to the die. Furthermore, while the use of stacked ceramic layers is known, it is difficult to incorporate more than one layer in a plastic package due to difficulties and added expense in attempting to mold such a structure.
It would, therefore, be desirable to provide a plastic-encapsulated package for an integrated circuit which would provide both superior heat dissipation characteristics as well as providing improved noise-related electrical properties.